Semiconductor device and method for fabricating the same

ABSTRACT

A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides of the n-type diffused source and drain layers are formed with p-type impurity implanted regions having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 on PatentApplication No. 2004-138010 filed in Japan on May 7, 2004, the entirecontents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

(a) Fields of the Invention

The present invention relates to semiconductor devices which have MIStransistors capable of accomplishing a further miniaturization andoperable at high speed and with low power consumption, and to methodsfor fabricating such a device.

(b) Description of Related Art

Accompanied with high integration of semiconductor integrated circuits,miniaturization of MIS transistors in the circuits is demanded. Toaccomplish this miniaturization, MIS transistors are required which havea heavily-doped source and drain structure with shallow junctions ofsource and drain regions (see, for example, Japanese Unexamined PatentPublication No. H11-261069).

Hereinafter, an example of conventional methods for fabricating asemiconductor device with a MIS transistor will be described withreference to the accompanying drawings.

FIGS. 12A to 12E show sectional structures of a conventionalsemiconductor device in the order of its fabrication process steps.

First, in the step shown in FIG. 12A, boron (B) ions serving as a p-typeimpurity are implanted into a semiconductor substrate 101 made of p-typesilicon on an implantation condition of an implantation energy of 10 keVand a dose of 2×10¹² ions/cm². Thereafter, thermal treatment isperformed to form a p-type diffused channel layer 102 in a channelformation region of the semiconductor substrate 101.

Next, in the step shown in FIG. 12B, a gate oxide film 103 is formed onthe semiconductor substrate 101 and subsequently a gate electrode 104 ofpolysilicon is formed on the gate oxide film 103.

Then, in the step shown in FIG. 12C, using the gate electrode 104 as amask, arsenic (As) ions serving as an n-type impurity are implanted intothe semiconductor substrate 101 to form n-type implanted extensionlayers 105A. Subsequently, using the gate electrode 104 as a mask, boron(B) ions serving as a p-type impurity are implanted into thesemiconductor substrate 101 to form p-type implanted pocket layers 106A.

In the step shown in FIG. 12D, an insulating film is deposited over thesemiconductor substrate 101, and then the deposited insulating film issubjected to an anisotropic etching to form sidewalls 107 on sidesurfaces of the gate electrode 104.

Next, in the step shown in FIG. 12E, using the gate electrode 104 andthe sidewalls 107 as a mask, arsenic ions serving as an n-type impurityare implanted into the semiconductor substrate 101. Thereafter, thesemiconductor substrate 101 is subjected to thermal treatment to formn-type diffused source and drain layers 108 in regions of thesemiconductor substrate 101 located below respective sides of thesidewalls 107. In this treatment, n-type diffused extension layers 105made by diffusion of the n-type implanted extension layers 105A areformed in regions of the semiconductor substrate 101 located below thesidewalls 107 and between the n-type diffused source and drain layers108 and the p-type diffused channel layer 102, respectively, and p-typediffused pocket layers 106 made by diffusion of the p-type implantedpocket layer 106A are formed in regions of the semiconductor substrate101 located below the n-type diffused extension layers 105,respectively.

In order to miniaturize the MIS transistor without manifesting a shortchannel effect, the conventional fabrication methods as described abovetend to lower the implantation energy of the impurity ion for formingthe n-type diffused extension layers 105 and increase the temperature ofthe thermal treatment for activation.

SUMMARY OF THE INVENTION

The above-described conventional method for fabricating a semiconductordevice with a MIS transistor, however, has the following problems.

First, in the step shown in FIG. 12E, using the gate electrode 104 andthe sidewalls 107 as a mask, a high dose of arsenic ions for forming thesource and drain regions are implanted into the semiconductor substrate101, and then thermal treatment for activation is performed at a hightemperature. In this case, transient enhanced diffusion (TED) is inducedin the impurity atoms (arsenic) forming the n-type diffused source anddrain layer 108, so that the resulting impurity atoms diffuse in a deepregion within the semiconductor substrate 101. This causes a problemthat a desired impurity profile cannot be provided. Note that thetransient enhanced diffusion refers to abnormal diffusion in whichdiffusion of impurity atoms is enhanced by interaction of impurity atomswith excess point defects caused by damages mainly resulting fromfabrication processes such as ion implantation.

Second, if annealing at a temperature higher than required is performedin order to suppress TED of the impurity atoms implanted into the n-typediffused source and drain layer 108, impurity redistribution occurs inthe n-type diffused extension layer 105 having once been formedshallowly. This simultaneously causes a problem that the junctionthereof is made deep. The depth and shape of the junction of the n-typediffused extension layer 105 directly affect short channelcharacteristics and driving current of the semiconductor device.Therefore, in the thermal treatment process for activating the impurityof the n-type diffused source and drain layer 108, prevention ofredistribution of the impurity profile in the diffused extension layer105 is as important as control of the impurity profile of the source anddrain region 108.

FIG. 13 shows the lateral (the parallel direction with the substratesurface) impurity concentration profile of a portion of the n-typediffused source/drain layer 108 which is taken along the line XIII-XIIIin FIG. 12E. FIG. 13 plots the logarithm of the impurity concentrationin ordinate and the distance from the outer edge of the sidewall inabscissa. In FIG. 13, the alternate long and short dashed curverepresents the concentration of boron (B) implanted to form the p-typediffused channel layer 102 and the p-type diffused pocket layer 106,while the broken curve represents the concentration of arsenic (As)implanted to form the n-type diffused source and drain layer 108. Asunderstood from FIG. 13, in the conventional structure, inside of then-type diffused source and drain layer 108 has the following profile: inthe vicinity of the junction with the p-type diffused pocket layer 106,a segregation region in which boron is segregated and a region in whichthe boron concentration is decreased are formed by the field effectresulting from the pn junction, while away from the vicinity of thejunction, the boron concentration is equal to the channel concentrationemployed for implantation into the substrate (which includes pocketimplantation). Therefore, arsenic implanted to form the n-type diffusedsource and drain layer 108 has a sufficiently higher concentration thanboron implanted into the substrate, so that the implanted arsenic ishardly affected by the boron. This results in the occurrence of TED. Inaddition, excess point defects caused by the arsenic implantation forforming the n-type diffused source and drain layer 108 spread even intothe diffused channel layer 102 below the gate electrode 104 during thediffusion, and the excess point defects entering below the gateelectrode 104 would induce reverse short channel effect that increasesthe threshold voltage.

Third, as miniaturization of transistors proceeds to make the gatelengths thereof smaller, the implantation energy of arsenic ions forforming the n-type diffused source and drain layer 108 is reduced. Whenthis reduction is promoted, channeling arising in the <110>-orientedzone axis allows arsenic ions to enter even into the diffused channellayer 102 located below the gate electrode 104. Thus, the arsenic ionshaving entered also come to affect the short channel characteristics ofthe device.

As is apparent from the above, it is extremely difficult for theconventional method for fabricating a semiconductor device to form thediffused source and drain layers having a shallow junction and highimpurity concentration essential to miniaturization of MIS transistorsso that the layers have a desired impurity concentration andconcurrently entry of an impurity ion and impurity distribution of thediffused extension layer by TED are minimized.

In view of the conventional problems, an object of the present inventionis to miniaturize a semiconductor device by minimizing manifestation ofshort channel effect (and reverse short channel effect) accompanied withthe miniaturization and concurrently allowing the shapes of diffusedsource and drain layers to be made shallow in the depth direction andsmall in the lateral direction.

To attain the above object, in the present invention, a method forfabricating a semiconductor device is designed so that an impurityhaving a conductivity type opposite to the conductivity type of sourceand drain regions is implanted into the source and drain regions andthen thermal treatment is performed to make an impurity diffusion withimpurity pairs (ion pairs) of n-type and p-type impurities produced,thereby forming the source and drain region of low resistance with athermal budget reduced. By this method, the formed semiconductor deviceincludes in the source and drain region an impurity diffused layer of aconductivity type opposite to the conductivity type of the source anddrain regions. Note that “thermal budget” refers to the amount ofthermal treatment represented by the product of the heating temperatureand the heating time.

To be more specific, a semiconductor device according to the presentinvention is characterized by comprising: a semiconductor layer of afirst conductivity type; a gate insulating film formed on thesemiconductor layer; a gate electrode formed on the gate insulatingfilm; and diffused source and drain layers of a second conductivity typeformed in regions of the semiconductor layer located below sides of thegate electrode, respectively. This device is also characterized in thatinsides of the diffused source and drain layers are formed with impurityimplanted regions of the first conductivity type having a lower impurityconcentration than the diffused source and drain layers.

In the semiconductor device of the present invention, insides of thediffused source and drain layers of the second conductivity type areformed with the impurity implanted regions of the first conductivitytype having a lower impurity concentration than the diffused source anddrain layer. By this, in thermally diffusing the impurity ion of thesecond conductivity type implanted for formation of the diffused sourceand drain layer, the impurity ion of the second conductivity typecombines with the impurity ion of the first conductivity type implantedinto the impurity implanted region to produce an ion pair, therebysuppressing transient enhanced diffusion. Thus, the junction depth ofthe diffused source and drain layer becomes shallow to miniaturize thesemiconductor device with manifestation of short channel effectminimized.

Preferably, the semiconductor device of the present invention furthercomprises: diffused extension layers of the second conductivity typeformed in regions of the semiconductor layer located below the sides ofthe gate electrode and between the diffused source and drain layers,respectively; and diffused pocket layers of the first conductivity typeformed in regions of the semiconductor substrate located below thediffused extension layers, respectively, and the impurity concentrationof the impurity implanted region is higher than that of the diffusedpocket layer.

Preferably, the semiconductor device of the present invention furthercomprises a diffused channel layer of the first conductivity type formedin a region of the semiconductor layer located below the gate electrode,and the impurity concentration of the impurity implanted region ishigher than that of the diffused channel layer.

Preferably, in the semiconductor device of the present invention, theimpurity of the second conductivity type forming the diffused source anddrain layers is arsenic, and the impurity of the first conductivity typeforming the impurity implanted region is indium.

Preferably, in the semiconductor device of the present invention, thediffused source and drain layers contain an element belonging to thegroup IV at a higher concentration than that of the semiconductor layerlocated below the gate electrode.

A method for fabricating a semiconductor device according to the presentinvention is characterized by comprising: the step (a) of sequentiallyforming a gate insulating film and a gate electrode on a semiconductorlayer of a first conductivity type; the step (b) of forming sidewalls onside surfaces of the gate electrode; the step (c) of subjecting thesemiconductor layer to ion implantation of a first impurity of the firstconductivity type using the gate electrode and the sidewalls as a mask,thereby forming impurity implanted layers of the first conductivity typein regions of the semiconductor layer located below sides of thesidewalls; the step (d) of subjecting the semiconductor layer to ionimplantation of a second impurity of a second conductivity type usingthe gate electrode and the sidewalls as a mask, thereby formingimplanted source and drain layers of the second conductivity type inregions of the semiconductor layer located below the sides of thesidewalls; and the step (e) of subjecting, after the steps (c) and (d),the semiconductor layer to a first thermal treatment, thereby diffusingthe second impurity to form diffused source and drain layers of thesecond conductivity type in regions of the semiconductor layer locatedbelow the sides of the sidewalls. This device is also characterized inthat in the step (e), insides of the diffused source and drain layersare formed with impurity implanted regions of the first conductivitytype, respectively, which are made by diffusing the first impurity witha lower impurity concentration than that of the diffused source anddrain layers.

The method for fabricating a semiconductor device according to thepresent invention includes not only the step (d) of implanting thesecond impurity of the second conductivity type to form the implantedsource and drain layers of the second conductivity type, but also thestep (c) of implanting the first impurity of the first conductivity typeto form the impurity implanted layers. Therefore, in the subsequentfirst thermal treatment step (e), the first and second impurities havingdifferent conductivity types produce an impurity pair (ion pair). Byproducing an ionized pair (positive and negative ions) having polaritiesopposite to each other, the produced impurity pair is electricallyneutral and difficult to diffuse. This suppresses transient enhanceddiffusion of the second impurity. As a consequence of this, the diffusedsource and drain layers can be formed which have shallower junctionsthan the case where only the second impurity is implanted.

Preferably, the method for fabricating a semiconductor device accordingto the present invention further comprises, after the step (a) andbefore the step (b), the step (f) of subjecting the semiconductor layerto ion implantation of a third impurity of the second conductivity typeusing the gate electrode as a mask, thereby forming implanted extensionlayers of the second conductivity type in regions of the semiconductorlayer located below sides of the gate electrode, the step (g) ofsubjecting regions of the semiconductor layer located below the sides ofthe gate electrode to ion implantation of a fourth impurity of the firstconductivity type using the gate electrode as a mask, thereby formingimplanted pocket layers of the first conductivity type in thesemiconductor layer, and the step (h) of subjecting, after the steps (f)and (g), the semiconductor layer to a second thermal treatment, therebydiffusing the third impurity to form diffused extension layers of thesecond conductivity type in regions of the semiconductor layer locatedbelow the sides of the gate electrode, and simultaneously diffusing thefourth impurity to form diffused pocket layers of the first conductivitytype in regions of the semiconductor layer located below the diffusedextension layers, and the impurity concentration of the impurityimplanted region is higher than that of the diffused pocket layer. Withthis method, the diffused extension layers having the same conductivitytype as the diffused source and drain layers are formed in regions ofthe semiconductor layer located below the sides of the gate electrode,and the diffused pocket layers having the opposite conductivity type tothe diffused source and drain layers are formed below the diffusedextension layers. This reduces the resistance between the source and thedrain, and limits expansion of a depletion layer in the channel regionformed below the gate electrode.

Preferably, the method for fabricating a semiconductor device accordingto the present invention further comprises, before the step (a), thestep (i) of subjecting the semiconductor layer to ion implantation of afifth impurity of the first conductivity type to form an implantedchannel layer of the first conductivity type in the semiconductor layer,and then subjecting the semiconductor layer to a third thermaltreatment, thereby diffusing the fifth impurity to form a diffusedchannel layer of the first conductivity type in the semiconductor layer,and the impurity concentration of the impurity implanted region ishigher than that of the diffused channel layer.

Preferably, the method for fabricating a semiconductor device accordingto the present invention further comprises, after the step (b) andbefore the steps (c) and (d), the step (j) of subjecting thesemiconductor layer to ion implantation of a sixth impurity using thegate electrode and the sidewalls as a mask, thereby forming amorphouslayers in regions of the semiconductor layer located below sides of thesidewalls. With this method, the second impurity for the source anddrain formation carried out in the step (d) can be prevented fromchanneling in the depth direction of the semiconductor layer.Furthermore, in the case where the semiconductor layer is made of, forexample, silicon, the second impurity can also be prevented fromentering into the region below the gate electrode resulting fromchanneling in the <110>-oriented zone axis.

Preferably, in this case, in the step (j), the sixth impurity isimplanted by angled implantation having a predetermined angle withrespect to the normal to a main surface of the semiconductor layer. Withthis method, channeling in the <110>-oriented zone axis can besuppressed more certainly.

Preferably, in the method for fabricating a semiconductor deviceaccording to the present invention, the sixth impurity is a group IVelement. With this method, in the case where the semiconductor layer ismade of silicon, when the semiconductor layer is amorphized with thegroup IV element, the group IV element never exerts an electricalinfluence on the semiconductor layer after amorphization of thesemiconductor layer. This is because the group IV element iselectrically neutral.

Preferably, in the method for fabricating a semiconductor deviceaccording to the present invention, ion implantation of the secondimpurity is conducted at an implantation projected range equal to orlarger than the implantation projected range of the first impurity.

Preferably, in the method for fabricating a semiconductor deviceaccording to the present invention, the first impurity is indium.

Preferably, the method for fabricating a semiconductor device accordingto the present invention further comprises, after the step (d) andbefore the step (e), the step (k) of performing an extremelylow-temperature thermal treatment of a level at which the implantedimpurity does not diffuse, thereby restoring crystal damages due to theion implantation.

Preferably, in this case, the heating temperature of the extremelylow-temperature thermal treatment is from 400 to 700° C. inclusive. Sucha low heating temperature range from 400 to 700° C. inclusive is atemperature range in which solid phase epitaxial regrowth (SPER) of theamorphous layer occurs. Therefore, in this range, substantially onlyrestoration of crystal damages can be carried out with the impurity ionshardly diffused.

Preferably, the method for fabricating a semiconductor device accordingto the present invention further comprises, the step (l) of removing,after the step (e), the sidewalls and then subjecting the semiconductorlayer to ion implantation of a third impurity of the second conductivitytype using the gate electrode as a mask, thereby forming implantedextension layers of the second conductivity type in regions of thesemiconductor layer located below sides of the gate electrode; the step(m) of subjecting the semiconductor layer to ion implantation of afourth impurity of the first conductivity type using the gate electrodeas a mask, thereby forming implanted pocket layers of the firstconductivity type in regions of the semiconductor layer located belowthe sides of the gate electrode; and the step (n) of subjecting, afterthe steps (l) and (m), the semiconductor layer to a second thermaltreatment, thereby diffusing the third impurity to form diffusedextension layers of the second conductivity type in regions of thesemiconductor layer located below the sides of the gate electrode, andsimultaneously diffusing the fourth impurity to form diffused pocketlayers of the first conductivity type in regions of the semiconductorlayer located below the diffused extension layers, and the impurityconcentration of the impurity implanted region is higher than that ofthe diffused pocket layer.

As described above, in this method, the sidewalls are selectivelyremoved after formation of the diffused source and drain layers, andthen the diffused extension layers are formed using the gate electrodeas a mask. Therefore, unlike the case where the diffused extensionlayers are formed previously, this method can avoid the situation inwhich by the thermal treatment in the step (e) of activating theimpurity for source and drain formation, redistribution occurs in theimpurity contained in the diffused extension layer, thereby making thejunction depth thereof deep.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing the structure of a semiconductordevice according to a first embodiment of the present invention.

FIGS. 2A to 2E are sectional views showing a method for fabricating asemiconductor device according to the first embodiment of the presentinvention in the order of its fabrication process steps.

FIGS. 3A to 3D are sectional views showing the method for fabricating asemiconductor device according to the first embodiment of the presentinvention in the order of its fabrication process steps.

FIG. 4A is a graph showing the lateral impurity concentration profile ofa portion of an n-type diffused source/drain layer which is taken alongthe line IVa-IVa in FIG. 2D.

FIG. 4B is a graph showing results of simulations of impurity profilesof arsenic obtained after thermal treatment and from processes with andwithout indium implantation for producing ion pairs.

FIGS. 5A to 5E are sectional views showing process steps of a method forfabricating a semiconductor device according to a second embodiment ofthe present invention.

FIGS. 6A to 6E are sectional views showing process steps of the methodfor fabricating a semiconductor device according to the secondembodiment of the present invention.

FIGS. 7A to 7D are sectional views showing process steps of a method forfabricating a semiconductor device according to a third embodiment ofthe present invention.

FIGS. 8A to 8C are sectional views showing process steps of the methodfor fabricating a semiconductor device according to the third embodimentof the present invention.

FIG. 9A is a graph showing the lateral impurity concentration profile ofa portion of an n-type diffused source/drain layer which is taken alongthe line IXa-IXa in FIGS. 7D, 8B, 8C, 11A, 11C, and 11D. FIG. 9B is agraph showing results of simulations of impurity profiles of arsenicobtained after thermal treatment and from processes with and withoutindium implantation for producing ion pairs.

FIGS. 10A to 10D are sectional views showing process steps of a methodfor fabricating a semiconductor device according to a fourth embodimentof the present invention.

FIGS. 11A to 11D are sectional views showing process steps of the methodfor fabricating a semiconductor device according to the fourthembodiment of the present invention.

FIGS. 12A to 12E are sectional views showing process steps of aconventional method for fabricating a semiconductor device.

FIG. 13 is a graph showing the lateral impurity concentration profile ofa portion of an n-type diffused source/drain layer which is taken alongthe line XIII-XIII in FIG. 12E.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

A first embodiment of the present invention will be described withreference to the accompanying drawings.

FIG. 1 is a view of a semiconductor device according to the firstembodiment of the present invention, which shows a cross-sectionalstructure of an n-channel type MIS transistor.

Referring to FIG. 1, a gate insulating film 14 is selectively formed ona main surface of a semiconductor substrate 11 of, for example, p-typesilicon, and a gate electrode 15 is selectively formed on the gateinsulating film 14. Insulating sidewalls 18 are formed on both sidesurfaces of the gate insulating film 14 and the gate electrode 15.

A p-type diffused channel layer 12 is formed in a region of thesemiconductor substrate 11 located below the gate insulating film 14.N-type diffused extension layers 16 are selectively formed in regions ofthe semiconductor substrate 11 located below the sidewalls 18,respectively, and p-type diffused pocket layers 17 are selectivelyformed below the n-type diffused extension layers 16, respectively.

In regions of the semiconductor substrate 11 located below sides of thesidewalls 18, n-type diffused source and drain layers 20 are formed tohave deeper junctions than the p-type diffused channel layer 12 and toconnect inner edges thereof to the n-type diffused extension layers 16and the p-type diffused pocket layers 17, respectively.

The first embodiment is characterized in that insides of the n-typediffused source and drain layers 20 are formed with p-type impurityimplanted regions 19, respectively, made by implanting a p-type impuritywith a lower impurity concentration than the concentration of theimpurity contained in the n-type diffused source and drain layers 20. Inthis embodiment, for example, arsenic (As) is introduced into the n-typediffused source and drain layers 20, while, for example, indium (In) isimplanted into the p-type impurity implanted region 19. The impurityconcentration of the p-type impurity implanted region 19 is set higherthan those of the p-type diffused channel layer 12 and the p-typediffused pocket layer 17.

As described above, in the semiconductor device according to the firstembodiment, the insides of the n-type diffused source and drain layers20 are formed with the p-type impurity implanted regions 19 having alower p-type impurity concentration than the impurity concentration ofthe n-type diffused source and drain layers 20. Thus, when arsenic ionsimplanted to form the n-type diffused source and drain layers 20 arethermally diffused, the arsenic ions serving as a donor and indium ionsserving as an acceptor produce ion pairs electrically neutral. By this,it becomes difficult for the indium ions to diffuse, so that the n-typediffused source and drain layers 20 having shallow junctions can beformed. Since the junctions of the n-type diffused source and drainlayers 20 can be made shallow, miniaturization of the MIS transistor canbe attained.

A fabrication method of the MIS transistor constructed above will bedescribed below with reference to the accompanying drawings.

FIGS. 2A to 2E and FIGS. 3A to 3D show sectional structures of thefabrication method of a semiconductor device according to the firstembodiment of the present invention in the order of its fabricationprocess steps.

First, in the step shown in FIG. 2A, into a channel formation region ofthe semiconductor substrate 11 made of p-type silicon, indium (In) ionsserving as a p-type impurity are implanted on an implantation conditionof an implantation energy of 70 keV and a dose of 8×10¹² ions/cm².Thereby, a p-type implanted channel layer 12A is formed in the upperportion of the semiconductor substrate 11.

Next, in the step shown in FIG. 2B, on a p-well formation region of thesemiconductor substrate 11, a first ion implantation of boron (B) ionsserving as a p-type impurity is conducted on a first implantationcondition of an implantation energy of 100 keV and a dose of 1×10¹³ions/cm². Subsequently, a second ion implantation thereof is conductedon a second implantation condition of an implantation energy of 250 keVand a dose of 1×10¹³ ions/cm². Thereby, a p-type implanted well layer13A is formed in a region of the semiconductor substrate 11 locatedbelow the p-type implanted channel layer 12A. Note that the ionimplantation into the channel layer may be conducted using a so-calledrotating implantation made in such a manner that the dose is dividedinto smaller doses and the divided doses of impurity ions are implantedsymmetrically within the wafer surface, at different implantationangles, and in several times. In the first embodiment, the implantationinto the channel layer is conducted before the implantation into thewell layer, but the implantation into the well layer may be conductedbefore the implantation into the channel layer.

In the step shown in FIG. 2C, subsequently to the formation of thep-type implanted channel layer 12A and the p-type implanted well layer13A, the semiconductor substrate 11 is heated to about 850 to 1050° C.at a heating rate of about 100° C./sec or more, preferably at a heatingrate of about 200° C./sec. After the heating, a first rapid thermalannealing (RTA) is performed either with the peak temperature thereofkept for about 10 seconds at the maximum or with the peak temperaturenot kept. This RTA forms the p-type diffused channel layer 12 and ap-type diffused well layer 13 in the upper portion of the semiconductorsubstrate 11. Note that the RTA with the peak temperature not kept meansthat the thermal treatment temperature is lowered on reaching the peaktemperature.

Subsequently, in the step shown in FIG. 2D, the gate insulating film 14of silicon oxide having a thickness of about 1.5 nm is selectivelyformed on the main surface of the semiconductor substrate 11. On thegate insulating film 14, the gate electrode 15 is selectively formedwhich is made of polysilicon or polymetal having a thickness of about150 nm.

In the step shown in FIG. 2E, using the gate electrode 15 as a mask,arsenic (As) ions serving as an n-type impurity are implanted into thesemiconductor substrate 11 on an implantation condition of animplantation energy of 2 keV and a dose of 2×10¹⁴ ions/cm², therebyforming n-type implanted extension layers 16A. Further, using the gateelectrode 15 as a mask, boron (B) ions serving as a p-type impurity areimplanted into the semiconductor substrate 11 on an implantationcondition of an implantation energy of 10 keV and a dose of 1×10¹³ions/cm², thereby forming p-type implanted pocket layers 17A.

Next, in the step shown in FIG. 3A, the semiconductor substrate 11 isheated to about 850 to 1050° C. at a heating rate of about 200° C./sec.After the heating, a second rapid thermal annealing is performed eitherwith the peak temperature thereof kept for about 10 seconds at themaximum or with the peak temperature not kept. The second rapid thermalannealing activates arsenic ions contained in the n-type implantedextension layers 16A to form, in regions of the semiconductor substrate11 located below both sides of the gate electrode 15, the n-typediffused extension layers 16 having relatively shallow junctions. Thisannealing also activates boron ions contained in the p-type implantedpocket layers 17A to form, below the n-type diffused extension layers16, the p-type diffused pocket layers 17 having a higher impurityconcentration than the p-type diffused channel layer 13.

In the step shown in FIG. 3B, by chemical vapor deposition (CVD) or thelike, a silicon nitride film having a thickness of about 50 nm isdeposited over the entire surface of the semiconductor substrate 11including the gate electrode 15. The deposited silicon nitride film isanisotropically etched to form the sidewalls 18 of silicon nitride onthe side surfaces of the gate electrode 15. The sidewalls 18 may be madenot of silicon nitride but of a single-layer film of silicon oxide, alaminate film composed of a silicon oxide film having an L-shaped crosssection and a silicon nitride film having a plate-like cross section onthe silicon oxide film, or the like. An offset spacer may be formedbetween each of the sidewalls 18 and the gate electrode 15.

Thereafter, in the step shown in FIG. 3C, using the gate electrode 15and the sidewalls 18 as a mask, indium ions serving as a p-type impurityare implanted into the semiconductor substrate 11 on an implantationcondition of an implantation energy of 10 keV and a dose of 1×10¹⁴ions/cm², thereby forming p-type ion implanted layers 19A. Subsequently,using the gate electrode 15 and the sidewalls 18 as a mask, arsenic ionsserving as an n-type impurity are implanted into the semiconductorsubstrate 11 on an implantation condition of an implantation energy of15 keV and a dose of 3×10¹⁵ ions/cm², thereby forming n-type implantedsource and drain layers 20A. Into the n-type implanted source and drainlayers 20A, arsenic ions are implanted which have a deeper implantationdepth and a higher concentration than the p-type ion implanted layer19A. Although not shown, in order to release an electric field in thesource and drain region, phosphorus (P) ions serving as an n-typeimpurity may be additionally implanted after the implantation of arsenicions on an implantation condition of an implantation energy of 20 keVand a dose of 1×10¹³ ions/cm². Since the surface of the semiconductorsubstrate 11 and its vicinity are amorphized by the implantations ofindium and a high dose of arsenic, the subsequent implantation ofphosphorus ions for releasing the electric field has an implantationprofile with a channeling greatly suppressed by the pre-amorphouseffect. For the n-type implanted source and drain layers 20A, use may bemade of phosphorus ions instead of arsenic ions.

In the step shown in FIG. 3D, the semiconductor substrate 11 is heatedto about 850 to 1000° C. at a heating rate of about 200 to 250° C./sec.After the heating, a third rapid thermal annealing is performed eitherwith the peak temperature thereof kept for about 10 seconds at themaximum or with the peak temperature not kept. The third rapid thermalannealing activates arsenic ions contained in the n-type implantedsource and drain layers 20A to form, in regions of the semiconductorsubstrate 11 located below the sides of the sidewalls 18, the n-typediffused source and drain layers 20. By the formation of the n-typediffused source and drain layers 20, the n-type diffused extensionlayers 16 and the p-type diffused pocket layers 17 are also formedbetween the p-type diffused channel layer 12 below the gate electrode 15and the n-type diffused source and drain layers 20. Each of the n-typediffused source and drain layers 20 has a junction connected to then-type diffused extension layer 16 and made deeper than the n-typediffused extension layer 16. In this state, inside each of the n-typediffused source and drain layers 20, the p-type impurity implantedregion 19 shown by the broken curve is embedded which is formed from thep-type ion implanted layer 19A. The p-type impurity concentration of thep-type impurity implanted region 19 is lower than the n-type impurityconcentration of the n-type diffused source and drain layers 20, so thatthe p-type impurity implanted region 19 will not be formed in thestructure of a p-type impurity diffused layer.

FIG. 4A shows the lateral (the parallel direction with the substratesurface) impurity concentration profile of a portion of the n-typediffused source/drain layer 20 which is taken along the line IVa-IVa inFIG. 3D. FIG. 4A plots the logarithm of the impurity concentration inordinate and the distance from the outer edge of the sidewall inabscissa. In FIG. 4A, the solid curve represents the concentration ofindium contained in the p-type impurity region 19 and implanted into thesource and drain formation region according to the present invention,while the broken curve represents the concentration of arsenic containedin the n-type diffused source and drain layers 20. For comparisonpurposes, the concentration of boron introduced into the source anddrain formation region during the conventional formation of the diffusedpocket layer is represented by the alternate long and short dashedcurve. As shown in FIG. 4A, indium that is a p-type impurity for thep-type impurity region 19 introduced within the n-type diffused sourceand drain layers 20 has a higher concentration than boron introduced bythe conventional formation of the p-type diffused pocket layer. Thisindium interacts with arsenic to suppress arsenic diffusion. Note thatFIG. 4A shows only the indium concentration as the present invention.However, in actuality, boron implantation forms the p-type diffusedpocket layer 17 similarly to the conventional example, so that the sumof the indium concentration and the boron concentration of the p-typediffused pocket layer 17 is the total concentration of the p-typeimpurity in this portion.

As described above, according to the first embodiment, in the step shownin FIG. 3C, the n-type implanted source and drain layers 20A for formingthe n-type diffused source and drain layers 20 and the p-type ionimplanted layers 19A having a lower impurity concentration than then-type implanted source and drain layers 20A are formed, and then in thestep shown in FIG. 3D, the third rapid thermal annealing for activatingarsenic ions in the n-type implanted source and drain layers 20A andindium ions in the p-type ion implanted layer 19A is performed. Since,in this treatment, the impurity concentration of the n-type implantedsource and drain layers 20A is higher than that of the p-type ionimplanted layer 19A, the n-type diffused source and drain layers 20 canbe formed certainly.

Ionized donor and acceptor atoms have the property of being electricallyattracted to each other by thermal treatment to produce an ion pair. Bythis property, ionized arsenic in the n-type implanted source and drainlayers 20A and ionized indium in the p-type ion implanted layer 19Aproduce an ion pair, which suppresses transient enhanced diffusion ofarsenic. Therefore, a diffusion layer can be formed which has ashallower junction than the case where only an n-type impurity isimplanted.

FIG. 4B shows results of simulations of the impurity profiles of arsenicobtained after the thermal treatment and from the processes with andwithout the indium implantation for producing ion pairs. From FIG. 4B,it is found that since indium for forming ion pairs is implanted in thepresent invention, the junction of arsenic in the present invention isshallower than that of the conventional case where indium for formingion pairs is not implanted.

Thus, the ion pair of arsenic and indium suppresses arsenic diffusion,which eliminates the necessity to set the thermal treatment foractivation for forming the n-type diffused source and drain layers 20 ata temperature higher than required. Moreover, in the thermal treatmentstep, the time for which the heated state is kept can be reduced, sothat the activation process can be carried out with a low thermalbudget. Furthermore, the step of activating the impurity for source anddrain formation can be carried out with a low thermal budget, which alsoavoids the conventional drawback that by the thermal treatment in thisstep, redistribution of the impurity occurs in the diffused extensionlayer having once been formed shallowly, thereby making the junctionthereof deep.

Moreover, an element with a relatively large mass number, such asindium, is used as a p-type impurity for combining with an impurity forsource and drain formation to produce an ion pair. Therefore, even at alow dose, the source and drain formation region of the semiconductorsubstrate 11 can be amorphized. Thus, by implanting indium for ion pairproduction prior to the ion implantation of arsenic for source and drainregion formation, the implanted indium ions also serve as an impurityfor implantation for pre-amorphization. This pre-amorphous effectsuppresses channeling of arsenic to be implanted subsequently, so thatthe implantation profile of arsenic can be made shallow. Duringrestoration of the crystal of the amorphous layer, the layer is in themeta-stable state in which the solubility limit of the containedimpurity is higher than that of the impurity contained in the crystallayer. Consequently, by this pre-amorphous effect, the impurity profileof arsenic created by the thermal diffusion for activation can obtain ashallow junction.

It is known that indium strongly segregates to a dislocation loop defectlayer. Therefore, by forming the p-type ion implanted layers 19A withindium ions implanted therein within the n-type implanted source anddrain layers 20A with arsenic ions implanted, the indium is trapped intothe dislocation loop defect layer. This suppresses transient enhanceddiffusion of arsenic caused by releasing interstitial silicon from thedislocation loop defect layer.

As is apparent from the above, with the method for fabricating asemiconductor device according to the first embodiment, the n-typediffused source and drain layers 20 with a shallow junction can beformed certainly while redistribution of the impurity in the n-typediffused extension layer 16 is suppressed.

Moreover, indium ions with a relatively large mass number are used forformation of the p-type diffused channel layer 12. Therefore, a regionof the p-type diffused channel layer 12 located around the substratesurface has a decreased impurity concentration, while a region thereoflocated slightly deeper than the substrate surface has an increasedimpurity concentration. That is to say, a retrograde impurity profilecan be provided in this layer. This prevents a decrease in carriermobility mainly resulting from impurity dispersion and thereforeminimizes manifestation of short channel effect. As a result, thetransistor in the device can be miniaturized reliably.

Second Embodiment

A second embodiment of the present invention will be described belowwith reference to the accompanying drawings.

FIGS. 5A to 5E and FIGS. 6A to 6E show sectional structures of afabrication method of a semiconductor device according to the secondembodiment of the present invention in the order of its fabricationprocess steps. Also in the second embodiment, description will be madeusing an n-channel type MIS transistor.

First, in the step shown in FIG. 5A, into a channel formation region ofa semiconductor substrate 11 made of p-type silicon, indium (In) ionsserving as a p-type impurity are implanted on an implantation conditionof an implantation energy of 70 keV and a dose of 8×10¹² ions/cm².Thereby, a p-type implanted channel layer 12A is formed.

Next, in the step shown in FIG. 5B, on a p-well formation region of thesemiconductor substrate 11, a first ion implantation of boron (B) ionsserving as a p-type impurity is conducted on a first implantationcondition of an implantation energy of 100 keV and a dose of 1×10¹³ions/cm². Subsequently, a second ion implantation thereof is conductedon a second implantation condition of an implantation energy of 250 keVand a dose of 1×10¹³ ions/cm². Thereby, a p-type implanted well layer13A is formed in a region of the semiconductor substrate 11 locatedbelow the p-type implanted channel layer 12A. Note that the ionimplantation into the channel layer may be conducted using a so-calledrotating implantation made in such a manner that the dose is dividedinto smaller doses and the divided doses of impurity ions are implantedsymmetrically within the wafer surface, at different implantationangles, and in several times. In the second embodiment, the implantationinto the channel layer is conducted before the implantation into thewell layer, but the implantation into the well layer may be conductedbefore the implantation into the channel layer.

In the step shown in FIG. 5C, subsequently to the formation of thep-type implanted channel layer 12A and the p-type implanted well layer13A, the semiconductor substrate 11 is heated to about 850 to 1050° C.at a heating rate of about 100° C./sec or more, preferably at a heatingrate of about 200° C./sec. After the heating, a first rapid thermalannealing (RTA) is performed either with the peak temperature thereofkept for about 10 seconds at the maximum or with the peak temperaturenot kept. This RTA forms a p-type diffused channel layer 12 and a p-typediffused well layer 13 in the upper portion of the semiconductorsubstrate 11.

Subsequently, in the step shown in FIG. 5D, a gate insulating film 14 ofsilicon oxide having a thickness of about 1.5 nm is selectively formedon the semiconductor substrate 11. On the gate insulating film 14, agate electrode 15 is selectively formed which is made of polysilicon orpolymetal having a thickness of about 150 nm.

In the step shown in FIG. 5E, using the gate electrode 15 as a mask,arsenic (As) ions serving as an n-type impurity are implanted into thesemiconductor substrate 11 on an implantation condition of animplantation energy of 2 keV and a dose of 2×10¹⁴ ions/cm², therebyforming n-type implanted extension layers 16A. Further, using the gateelectrode 15 as a mask, boron ions serving as a p-type impurity areimplanted into the semiconductor substrate 11 on an implantationcondition of an implantation energy of 10 keV and a dose of 1×10¹³ions/cm², thereby forming p-type implanted pocket layers 17A.

Next, in the step shown in FIG. 6A, the semiconductor substrate 11 isheated to about 850 to 1050° C. at a heating rate of about 200° C./sec.After the heating, a second rapid thermal annealing is performed eitherwith the peak temperature thereof kept for about 10 seconds at themaximum or with the peak temperature not kept. The second rapid thermalannealing activates arsenic ions contained in the n-type implantedextension layers 16A to form, in regions of the semiconductor substrate11 located below both sides of the gate electrode 15, n-type diffusedextension layers 16 having relatively shallow junctions. This annealingalso activates boron ions contained in the p-type implanted pocketlayers 17A to form, below the n-type diffused extension layers 16,p-type diffused pocket layers 17 having a higher impurity concentrationthan the p-type diffused channel layer 13.

In the step shown in FIG. 6B, by a CVD method or the like, a siliconnitride film having a thickness of about 50 nm is deposited over theentire surface of the semiconductor substrate 11 including the gateelectrode 15. The deposited silicon nitride film is anisotropicallyetched to form sidewalls 18 of a silicon nitride film on the sidesurfaces of the gate electrode 15. The sidewalls 18 may be made not of asilicon nitride film but of a single-layer film of silicon oxide, alaminate film composed of a silicon oxide film having an L-shaped crosssection and a silicon nitride film having a plate-like cross section onthe silicon oxide film, or the like. An offset spacer may be formedbetween each of the sidewalls 18 and the gate electrode 15.

Next, in the step shown in FIG. 6C, using the gate electrode 15 and thesidewalls 18 as a mask, germanium (Ge) ions belonging to the group IVare implanted into the semiconductor substrate 11 on an implantationcondition of an implantation energy of 100 keV and a dose of 1×10¹⁵ions/cm², thereby forming amorphous layers 21 in the source and drainformation regions of the semiconductor substrate 11, respectively. Theamorphous layers 21 are desirably formed to have deeper depths thanimplanted source and drain layers that will be formed in a later step.In this formation, the group IV element, other than germanium, formingthe amorphous layer 21 may be silicon (Si) that has no electricalinfluence on the semiconductor substrate 11 as in the case of usinggermanium. If, in this step, silicon is used to form the amorphous layer21, the concentration of implanted silicon is added to the siliconconcentration of the semiconductor substrate 11. Therefore, the siliconconcentration of the region forming the amorphous layer 21 is higherthan that of the region of the semiconductor substrate 11 locatedimmediately below the gate electrode 15.

Thereafter, in the step shown in FIG. 6D, using the gate electrode 15and the sidewalls 18 as a mask, indium ions serving as a p-type impurityare implanted into the amorphous layers 21 formed in the semiconductorsubstrate 11 on an implantation condition of an implantation energy of10 keV and a dose of 1×10¹⁴ ions/cm², thereby forming p-type ionimplanted layers 19A. Subsequently, using the gate electrode 15 and thesidewalls 18 as a mask, arsenic ions serving as an n-type impurity areimplanted into the amorphous layers 21 formed in the semiconductorsubstrate 11 on an implantation condition of an implantation energy of15 keV and a dose of 3×10¹⁵ ions/cm², thereby forming n-type implantedsource and drain layers 20A. Into the n-type implanted source and drainlayers 20A, arsenic ions are implanted which have a deeper implantationdepth and a higher concentration than the p-type ion implanted layer19A. Although not shown, in order to release an electric field in thesource and drain region, phosphorus (P) ions serving as an n-typeimpurity may be additionally implanted after the implantation of arsenicions on an implantation condition of an implantation energy of 20 keVand a dose of 1×10¹³ ions/cm². Since the amorphous layer 21 is formed inthe semiconductor substrate 11, the implantation of phosphorus ions forreleasing the electric field has an implantation profile with achanneling greatly suppressed by the pre-amorphous effect. For then-type implanted source and drain layers 20A, use may be made ofphosphorus ions instead of arsenic ions.

In the step shown in FIG. 6E, the semiconductor substrate 11 formed withthe amorphous layers 21, the p-type ion implanted layers 19A, and then-type implanted source and drain layers 20A is heated to about 400 to700° C., more preferably to about 400 to 600° C. After the heating, athird thermal treatment at an extremely low temperature (referredhereinafter to as an extremely low-temperature thermal treatment) isperformed on the semiconductor substrate 11 in the state in which thetemperature the heated substrate 11 has reached is kept for from severalseconds to about 10 hours at the maximum. The treatment temperature ofthis treatment is sufficiently low, so that impurity diffusion resultingfrom transient enhanced diffusion hardly occurs and only restoration ofcrystal damages caused by ion implantation and of the amorphized crystalproceeds. As a result, the positions of junctions are almost the same asthe positions thereof located immediately after the respective ionimplantations.

Subsequently to the third extremely low-temperature thermal treatment,the semiconductor substrate 11 is heated to about 850 to 1000° C. at aheating rate of about 200 to 250° C./sec. After the heating, a fourthrapid thermal annealing is performed either with the peak temperaturethereof kept for about 10 seconds at the maximum or with the peaktemperature not kept. The fourth rapid thermal annealing activatesarsenic ions contained in the n-type implanted source and drain layers20A to form, in regions of the semiconductor substrate 11 located belowthe sides of the sidewalls 18, n-type diffused source and drain layers20. By the formation of the n-type diffused source and drain layers 20,the n-type diffused extension layers 16 and the p-type diffused pocketlayers 17 are also formed between the p-type diffused channel layer 12below the gate electrode 15 and the n-type diffused source and drainlayers 20. Each of the n-type diffused source and drain layers 20 has ajunction connected to the n-type diffused extension layer 16 and madedeeper than the n-type diffused extension layer 16. In this state,inside each of the n-type diffused source and drain layers 20, thep-type impurity implanted region 19 shown by the broken curve isembedded which is formed from the p-type ion implanted layer 19A. Thep-type impurity concentration of the p-type impurity implanted region 19is lower than the n-type impurity concentration of the n-type diffusedsource and drain layers 20, so that the p-type impurity implanted region19 will not be formed in the structure of a p-type impurity diffusedlayer. The fourth rapid thermal annealing, such as spike RTA, laserannealing, and flash lamp annealing, can be performed to enhanceactivation of impurities for which the activation only by the thirdextremely low-temperature thermal treatment is inadequate.

As described above, according to the second embodiment, in the stepshown in FIG. 6C, the amorphous layers 21 are formed in the source anddrain formation region, and then in the step shown in FIG. 6D, thep-type ion implanted layers 19A and the n-type implanted source anddrain layers 20A are formed. The formed amorphous layer 21 suppresseschanneling of arsenic in forming the n-type implanted source and drainlayers 20A, whereby the n-type implanted source and drain layers 20Ahaving a shallow impurity profile can be formed.

Thereafter, in the step shown in FIG. 6E, subsequently to crystalrestoration by the third extremely low-temperature thermal treatment,the fourth rapid thermal annealing carries out activation. Thereby, theimplanted impurity can be activated with this impurity hardly diffused.As described above, during this activation, ionized donor and acceptoratoms have the property of being electrically attracted to each other bythe thermal treatment to produce an ion pair. By this property, ionizedarsenic in the n-type implanted source and drain layers 20A and ionizedindium in the p-type ion implanted layer 19A produce an ion pair, whichsuppresses transient enhanced diffusion of arsenic. Therefore, then-type diffused source and drain layers 20 can be formed which has ashallower junction than the case where only an n-type impurity isimplanted.

Thus, the ion pair suppresses arsenic diffusion, which eliminates thenecessity to set the thermal treatment performed subsequently to theextremely low-temperature thermal treatment and performed for activationfor forming the diffused source and drain layers at a temperature higherthan required. Moreover, in the thermal treatment, the time for whichthe heated state is kept can be reduced, so that the activation processcan be carried out with a low thermal budget. Furthermore, the step ofactivating the impurity for source and drain formation can be carriedout with a low thermal budget, which also avoids the conventionaldrawback that by the thermal treatment in this step, redistribution ofthe impurity occurs in the diffused extension layer having once beenformed shallowly, thereby making the junction thereof deep.

Moreover, since, in the step shown in FIG. 6E, the extremelylow-temperature thermal treatment is performed after the ionimplantation into the source and drain formation region, the amorphouslayer formed by high-dose implantation for pre-amorphization can berestored to a crystal layer. In this treatment, the thermal treatmenttemperature is sufficiently low. Therefore, only point defects disappearby diffusion and recombination, impurity diffusion resulting fromtransient enhanced diffusion hardly occurs, and only regrowth of theamorphous layer proceeds. It is known that under thermal treatmenttemperatures of about 400 to 700° C., more limitedly, about 400 to 600°C., within which the above-mentioned actions arise, solid phase regrowthoccurs in the amorphous layer. Thus, the junction of arsenic and indiumimplanted into the source and drain formation region can keep a shallowjunction that is almost the same as that made at the time of the ionimplantation. During restoration of the crystal of the amorphous layer,the layer is in the meta-stable state in which the solubility limit ofthe contained impurity is higher than that of the impurity contained inthe crystal layer.

Furthermore, since, in the step shown in FIG. 6C, germanium ionsbelonging to the group IV are implanted, the source and drain formationregion can be amorphized selectively and positively. Thus, the sourceand drain formation region is pre-amorphized before formation of then-type implanted source and drain layers 20A, so that not onlychanneling in the depth direction of the implantation profile of arsenicions implanted into the n-type implanted source and drain layers 20A,but also laterally struggling intrusion of arsenic ions into the regionbelow the gate electrode 15 resulting from channeling in the<110>-oriented zone axis can be suppressed.

Moreover, as described above, it is known that indium stronglysegregates to a dislocation loop defect layer. Therefore, by forming thep-type ion implanted layers 19A with indium ions implanted thereinwithin the n-type implanted source and drain layers 20A with arsenicions implanted, the indium is trapped into the dislocation loop defectlayer. This suppresses transient enhanced diffusion of arsenic caused byreleasing interstitial silicon from the dislocation loop defect layer.

As is apparent from the above, the n-type diffused source and drainlayers 20 with shallow junctions can be formed certainly whileredistribution of the impurity contained in the n-type diffusedextension layer 16 is prevented.

Moreover, indium ions with a relatively large mass number are used forformation of the p-type diffused channel layer 12. Therefore, a regionof the p-type diffused channel layer 12 located around the substratesurface has a decreased impurity concentration, while a region thereoflocated away from the substrate surface has an increased impurityconcentration. That is to say, a retrograde impurity profile can beprovided in this layer. This prevents a decrease in carrier mobilitymainly resulting from impurity dispersion and therefore minimizesmanifestation of short channel effect. As a result, the transistor inthe device can be miniaturized reliably.

Third Embodiment

A semiconductor device according to a third embodiment of the presentinvention will be described below with reference to the accompanyingdrawings.

FIGS. 7A to 7D and FIGS. 5A to 8C show sectional structures of afabrication method of a semiconductor device according to the thirdembodiment of the present invention in the order of its fabricationprocess steps. Also in the third embodiment, description will be madeusing an n-channel type MIS transistor.

First, in a similar manner to the first embodiment, as shown in FIG. 7A,a p-type diffused channel layer 12 and a p-type diffused well layer 13are formed in the upper portion of a semiconductor substrate 11 ofp-type silicon. Thereafter, a gate insulating film 14 of silicon oxidehaving a thickness of about 1.5 nm is selectively formed on a mainsurface of the semiconductor substrate 11, and on the gate insulatingfilm 14, a gate electrode 15 is selectively formed which is made ofpolysilicon or polymetal having a thickness of about 150 nm.

Next, in the step shown in FIG. 7B, by a CVD method or the like, asilicon nitride film having a thickness of about 50 nm is deposited overthe entire surface of the semiconductor substrate 11 including the gateelectrode 15. The deposited silicon nitride film is anisotropicallyetched to form first sidewalls 18A of silicon nitride on side surfacesof the gate electrode 15. The first sidewalls 18A may be made not ofsilicon nitride but of a single-layer film of silicon oxide, a laminatefilm composed of a silicon oxide film having an L-shaped cross sectionand a silicon nitride film having a plate-like cross section on thesilicon oxide film, or the like. An offset spacer may be formed betweeneach of the first sidewalls 18A and the gate electrode 15.

Subsequently, in the step shown in FIG. 7C, using the gate electrode 15and the first sidewalls 18A as a mask, indium ions serving as a p-typeimpurity are implanted into the semiconductor substrate 11 on animplantation condition of an implantation energy of 10 keV and a dose of1×10¹⁴ ions/cm², thereby forming p-type ion implanted layers 19A.Thereafter, using the gate electrode 15 and the first sidewalls 18A as amask, arsenic ions serving as an n-type impurity are implanted into thesemiconductor substrate 11 on an implantation condition of animplantation energy of 15 keV and a dose of 3×10¹⁵ ions/cm², therebyforming n-type implanted source and drain layers 20A. Into the n-typeimplanted source and drain layers 20A, the impurity is implanted whichhas a deeper implantation depth and a higher concentration than thep-type ion implanted layer 19A. Although not shown, in order to releasean electric field in the source and drain region, phosphorus (P) ionsserving as an n-type impurity may be additionally implanted after theimplantation of arsenic ions on an implantation condition of animplantation energy of 20 keV and a dose of 1×10¹³ ions/cm². Since thesurface of the semiconductor substrate 11 and its vicinity areamorphized by the implantations of indium and a high dose of arsenic,the subsequent implantation of phosphorus ions for releasing theelectric field has an implantation profile with a channeling greatlysuppressed by the pre-amorphous effect. For the n-type implanted sourceand drain layers 20A, use may be made of phosphorus ions instead ofarsenic ions.

In the step shown in FIG. 7D, the semiconductor substrate 11 is heatedto about 850 to 1000° C. at a heating rate of about 200 to 250° C./sec.After the heating, a first rapid thermal annealing is performed eitherwith the peak temperature thereof kept for about 10 seconds at themaximum or with the peak temperature not kept. The first rapid thermalannealing activates arsenic ions contained in the n-type implantedsource and drain layers 20A to form, in regions of the semiconductorsubstrate 11 located below the sides of the first sidewalls 18A, then-type diffused source and drain layers 20. In this state, inside eachof the n-type diffused source and drain layers 20, the p-type impurityimplanted region 19 shown by the broken curve is embedded which isformed from the p-type ion implanted layer 19A. The p-type impurityconcentration of the p-type impurity implanted region 19 is lower thanthe n-type impurity concentration of the n-type diffused source anddrain layers 20, so that the p-type impurity implanted region 19 willnot be formed in the structure of a p-type impurity diffused layer.

Next, in the step shown in FIG. 8A, the first sidewalls 18A areselectively removed by, for example, wet etching with a hot solution ofphosphoric acid. Then, using the gate electrode 15 as a mask, arsenic(As) ions serving as an n-type impurity are implanted into thesemiconductor substrate 11 on an implantation condition of animplantation energy of 2 keV and a dose of 2×10¹⁴ ions/cm², therebyforming n-type implanted extension layers 16A. Further, using the gateelectrode 15 as a mask, boron ions serving as a p-type impurity areimplanted into the semiconductor substrate 11 on an implantationcondition of an implantation energy of 10 keV and a dose of 1×10¹³ions/cm², thereby forming p-type implanted pocket layers 17A.

In the step shown in FIG. 8B, the semiconductor substrate 11 is heatedto about 850 to 1050° C. at a heating rate of about 200° C./sec. Afterthe heating, a second rapid thermal annealing is performed either withthe peak temperature thereof kept for about 10 seconds at the maximum orwith the peak temperature not kept. The second rapid thermal annealingactivates arsenic ions contained in the n-type implanted extensionlayers 16A to form, in regions of the semiconductor substrate 11 locatedbelow both sides of the gate electrode 15, n-type diffused extensionlayers 16 having relatively shallow junctions. This annealing alsoactivates boron ions contained in the p-type implanted pocket layers 17Ato form, below the n-type diffused extension layers 16, p-type diffusedpocket layers 17 having a higher impurity concentration than the p-typediffused channel layer 13. The n-type diffused extension layers 16 havejunctions which are connected to the n-type diffused source and drainlayers 20 and which are shallower than the n-type diffused source anddrain layers 20, respectively.

Subsequently, in the step shown in FIG. 8C, in a similar manner to thestep shown in FIG. 7B, second sidewalls 18B are formed again on the bothside surfaces of the gate electrode 15. Thus, in the third embodiment,the first sidewalls 18A are removed after formation of the n-typediffused source and drain layers 20, and the second sidewalls 18B areformed again after formation of the n-type diffused extension layer 16and the p-type diffused pocket layer 17. This eliminates thedisadvantage that the thickness (width) of the second sidewall 18Brestricts the dimensions in the gate length direction of the n-typediffused source and drain layers 20, the n-type diffused extension layer16, and the p-type diffused pocket layer 17. Therefore, the thickness(width) of the second sidewall 18B can be set freely. Also in thisembodiment, the second sidewalls 18B may be made not of silicon nitridebut of a single-layer film of silicon oxide, a laminate film composed ofa silicon oxide film having an L-shaped cross section and a siliconnitride film having a plate-like cross section on the silicon oxidefilm, or the like. An offset spacer may be formed between each of thesecond sidewalls 18B and the gate electrode 15.

FIG. 9A shows the lateral impurity concentration profile of a portion ofthe n-type diffused source/drain layer 20 which is taken along the lineIXa-IXa in FIGS. 7D, 8B and 8C. FIG. 9A plots the logarithm of theimpurity concentration in ordinate and the distance from the outer edgeof the sidewall in abscissa. In FIG. 9A, the solid curve represents theconcentration of indium contained in the p-type impurity region 19 andimplanted into the source and drain formation region according to thepresent invention, while the broken curve represents the concentrationof arsenic in the n-type diffused source and drain layers 20. Forcomparison purposes, the concentration of boron introduced into thesource and drain formation region during the conventional formation ofthe diffused pocket layer is represented by the alternate long and shortdashed curve. As shown in FIG. 9A, indium that is a p-type impurity forthe p-type impurity region 19 introduced within the n-type diffusedsource and drain layers 20 has a higher concentration than boronintroduced by the conventional formation of the p-type diffused pocketlayer. The introduced indium interacts with arsenic to suppress arsenicdiffusion.

As described above, according to the third embodiment, in the step shownin FIG. 7D, the n-type implanted source and drain layers 20A for formingthe n-type diffused source and drain layers 20 and the p-type ionimplanted layers 19A having a lower impurity concentration than then-type implanted source and drain layers 20A are formed prior toformation of the n-type diffused extension layers 16. Thereafter, in thestep shown in FIG. 8B, the second rapid thermal annealing is performedto activate arsenic ions in the n-type implanted source and drain layers20A and indium ions in the p-type ion implanted layer 19A. Since, inthis treatment, the impurity concentration of the n-type implantedsource and drain layers 20A is higher than that of the p-type ionimplanted layer 19A, the n-type diffused source and drain layers 20 canbe formed certainly.

As mentioned above, ionized arsenic in the n-type implanted source anddrain layers 20A and ionized indium in the p-type ion implanted layer19A produce an ion pair. The produced ion pair suppresses transientenhanced diffusion of arsenic, whereby the n-type diffused source anddrain layers 20 can be formed which has a shallower junction depth thanthe case where only an n-type impurity is implanted.

FIG. 9B shows results of simulations of the impurity profiles of arsenicobtained after the thermal treatment and from the processes with andwithout the indium implantation for producing ion pairs. From FIG. 9B,it is found that since indium for forming ion pairs is implanted in thepresent invention, the junction of arsenic in the present invention isshallower than that of the conventional case where indium for formingion pairs is not implanted.

Thus, the ion pair of arsenic and indium suppresses arsenic diffusion,which eliminates the necessity to set the thermal treatment foractivation for forming the n-type diffused source and drain layers 20 ata temperature higher than required. Moreover, in the thermal treatmentstep, the necessity to set the time for which the heated state is keptis eliminated, so that the activation process can be carried out with alow thermal budget.

Furthermore, the n-type diffused extension layer 16 is formed afterformation of the n-type diffused source and drain layers 20, which alsoavoids the situation in which by the thermal treatment in the step ofactivating the n-type impurity for source and drain formation,redistribution occurs in the impurity contained in the n-type diffusedextension layer 16 having been formed once, thereby making the junctiondepth thereof deep.

Moreover, if the gate electrode 15 is made of polysilicon or polymetal,an activation process for an impurity introduced in the polysiliconforming the gate electrode 15 can also be carried out by the formationstep of the diffused source and drain layers 20 to more fully activatethe polysilicon or the like forming the gate electrode 15.

As is apparent from the above, with the method for fabricating asemiconductor device according to the third embodiment, the n-typediffused source and drain layers 20 with shallow junctions can be formedcertainly while redistribution of the impurity in the n-type diffusedextension layer 16 is suppressed.

Moreover, indium ions with a relatively large mass number are used forformation of the p-type diffused channel layer 12. Therefore, a regionof the p-type diffused channel layer 12 located around the substratesurface has a decreased impurity concentration, while a region thereoflocated slightly deeper than the substrate surface has an increasedimpurity concentration. That is to say, a retrograde impurity profilecan be provided in this layer. This prevents a decrease in carriermobility mainly resulting from impurity dispersion and thereforeminimizes manifestation of short channel effect. As a result, thetransistor in the device can be miniaturized reliably.

Fourth Embodiment

A semiconductor device according to a fourth embodiment of the presentinvention will be described below with reference to the accompanyingdrawings.

FIGS. 10A to 10D and FIGS. 11A to 11D show sectional structures of afabrication method of a semiconductor device according to the fourthembodiment of the present invention in the order of its fabricationprocess steps. Also in the fourth embodiment, description will be madeusing an n-channel type MIS transistor.

First, in a similar manner to the first embodiment, as shown in FIG.10A, a p-type diffused channel layer 12 and a p-type diffused well layer13 are formed in the upper portion of a semiconductor substrate 11 ofp-type silicon. Thereafter, a gate insulating film 14 of silicon oxidehaving a thickness of about 1.5 nm is selectively formed on a mainsurface of the semiconductor substrate 11, and on the gate insulatingfilm 14, a gate electrode 15 is selectively formed which is made ofpolysilicon or polymetal having a thickness of about 150 nm.

Next, in the step shown in FIG. 10B, by a CVD method or the like, asilicon nitride film having a thickness of about 50 nm is deposited overthe entire surface of the semiconductor substrate 11 including the gateelectrode 15. The deposited silicon nitride film is anisotropicallyetched to form first sidewalls 18A of silicon nitride on side surfacesof the gate electrode 15. The first sidewalls 18A may be made not ofsilicon nitride but of a single-layer film of silicon oxide, a laminatefilm composed of a silicon oxide film having an L-shaped cross sectionand a silicon nitride film having a plate-like cross section on thesilicon oxide film, or the like. An offset spacer may be formed betweeneach of the first sidewalls 18A and the gate electrode 15.

Thereafter, in the step shown in FIG. 10C, using the gate electrode 15and the first sidewalls 18A as a mask, germanium (Ge) ions belonging tothe group IV are implanted into the semiconductor substrate 11 at animplantation energy of 100 keV, a dose of 1×10¹⁵ ions/cm², and a tileangle (implantation angle) of about 20 degrees with respect to thenormal to the substrate surface, thereby forming amorphous layers 21 insource and drain formation regions of the semiconductor substrate 11.The amorphous layers 21 are desirably formed to have a shallower depththan an implanted source and drain layers that will be formed in a laterstep. In addition, this angled implantation amorphizes also regions ofthe semiconductor substrate 11 located below the first sidewalls 18A, sothat entry of arsenic ions into the region below the gate electrode 15resulting from channeling in the <110>-oriented zone axis can besuppressed more certainly. Thus, even though the amorphous layer 21 isformed by angled implantation, the first sidewalls 18A covering sidesurfaces of the gate electrode 15 and the gate insulating film 14eliminates the possibility that side edges of the gate insulating film14 are damaged by the germanium ions. As a group IV element forming theamorphous layer 21, silicon (Si) may be used instead of germanium.

Subsequently, in the step shown in FIG. 10D, using the gate electrode 15and the first sidewalls 18A as a mask, indium ions serving as a p-typeimpurity are implanted into the amorphous layers 21 formed in thesemiconductor substrate 11 on an implantation condition of animplantation energy of 10 keV and a dose of 1×10¹⁴ ions/cm², therebyforming p-type ion implanted layers 19A. Subsequently, using the gateelectrode 15 and the first sidewalls 18A as a mask, arsenic ions servingas an n-type impurity are implanted into the amorphous layers 21 formedin the semiconductor substrate 11 on an implantation condition of animplantation energy of 15 keV and a dose of 3×10¹⁵ ions/cm², therebyforming n-type implanted source and drain layers 20A. Into the n-typeimplanted source and drain layers 20A, the impurity is implanted whichhas a deeper implantation depth and a higher concentration than thep-type ion implanted layer 19A. Although not shown, in order to releasean electric field in the source and drain region, phosphorus (P) ionsserving as an n-type impurity may be additionally implanted after theimplantation of arsenic ions on an implantation condition of animplantation energy of 20 keV and a dose of 1×10¹³ ions/cm². Since thesurface of the semiconductor substrate 11 and its vicinity areamorphized by the implantations of indium and a high dose of arsenic,the subsequent implantation of phosphorus ions for releasing theelectric field has an implantation profile with a channeling greatlysuppressed by the pre-amorphous effect. For the n-type implanted sourceand drain layers 20A, use may be made of phosphorus ions instead ofarsenic ions.

In the step shown in FIG. 11A, the semiconductor substrate 11 formedwith the amorphous layers 21, the p-type ion implanted layers 19A, andthe n-type implanted source and drain layers 20A is heated to about 400to 700° C., more preferably to about 400 to 600° C. After the heating, afirst extremely low-temperature thermal treatment is performed on thesemiconductor substrate 11 for from several seconds to about 10 hours atthe maximum. The treatment temperature of this treatment is sufficientlylow, so that impurity diffusion resulting from transient enhanceddiffusion hardly occurs. Therefore, only restoration of crystal damagescaused by ion implantation and of the amorphized crystal proceeds, andthe positions of junctions of the implanted layers are almost the sameas the positions thereof located immediately after the respective ionimplantations.

Subsequently to the first extremely low-temperature thermal treatmentunder an extremely low temperature, the semiconductor substrate 11 isheated to about 850 to 1000° C. at a heating rate of about 200 to 250°C./sec. After the heating, a second rapid thermal annealing (spike RTA,laser annealing, flash lamp annealing, or the like) is performed eitherwith the peak temperature thereof kept for about 10 seconds at themaximum or with the peak temperature not kept. The second rapid thermalannealing activates arsenic ions contained in the n-type implantedsource and drain layers 20A to form, in regions of the semiconductorsubstrate 11 located below the sides of the first sidewalls 18A, n-typediffused source and drain layers 20. In this state, inside each of then-type diffused source and drain layers 20, the p-type impurityimplanted region 19 shown by the broken curve is embedded which isformed from the p-type ion implanted layer 19A. The p-type impurityconcentration of the p-type impurity implanted region 19 is lower thanthe n-type impurity concentration of the n-type diffused source anddrain layers 20, so that the p-type impurity implanted region 19 willnot be formed in the structure of a p-type impurity diffused layer. Thesecond rapid thermal annealing can be performed to enhance activation ofimpurities for which the activation only by the first extremelylow-temperature thermal treatment is inadequate.

Next, in the step shown in FIG. 11B, the first sidewalls 18A areselectively removed by, for example, wet etching with a hot solution ofphosphoric acid. Then, using the gate electrode 15 as a mask, arsenic(As) ions serving as an n-type impurity are implanted into thesemiconductor substrate 11 on an implantation condition of animplantation energy of 2 keV and a dose of 2×10¹⁴ ions/cm², therebyforming n-type implanted extension layers 16A. Further, using the gateelectrode 15 as a mask, boron ions serving as a p-type impurity areimplanted into the semiconductor substrate 11 on an implantationcondition of an implantation energy of 10 keV and a dose of 1×10¹³ions/cm², thereby forming p-type implanted pocket layers 17A.

In the step shown in FIG. 11C, the semiconductor substrate 11 is heatedto about 850 to 1050° C. at a heating rate of about 200° C./sec. Afterthe heating, a third rapid thermal annealing is performed either withthe peak temperature thereof kept for about 10 seconds at the maximum orwith the peak temperature not kept. The third rapid thermal annealingactivates arsenic ions contained in the n-type implanted extensionlayers 16A to form, in regions of the semiconductor substrate 11 locatedbelow both sides of the gate electrode 15, n-type diffused extensionlayers 16 having relatively shallow junctions. This annealing alsoactivates boron ions contained in the p-type implanted pocket layers 17Ato form, below the n-type diffused extension layers 16, p-type diffusedpocket layers 17 having a higher impurity concentration than the p-typediffused channel layer 13. The n-type diffused extension layers 16 havejunctions which are connected to the n-type diffused source and drainlayers 20 and which are shallower than the n-type diffused source anddrain layers 20, respectively.

Subsequently, in the step shown in FIG. 11D, in a similar manner to thestep shown in FIG. 10B, second sidewalls 18B are formed again on theboth side surfaces of the gate electrode 15. Thus, in the fourthembodiment, the first sidewalls 18A are removed after formation of then-type diffused source and drain layers 20, and the second sidewalls 18Bare formed again after formation of the n-type diffused extension layer16 and the p-type diffused pocket layer 17. This eliminates thedisadvantage that the thickness (width) of the second sidewall 18Brestricts the dimensions in the gate length direction of the n-typediffused source and drain layers 20, the n-type diffused extension layer16, and the p-type diffused pocket layer 17. Therefore, the thickness(width) of the second sidewall 18B can be set freely. Also in thisembodiment, the second sidewalls 18B may be made not of silicon nitridebut of a single-layer film of silicon oxide, a laminate film composed ofa silicon oxide film having an L-shaped cross section and a siliconnitride film having a plate-like cross section on the silicon oxidefilm, or the like. An offset spacer may be formed between each of thesecond sidewalls 18B and the gate electrode 15.

FIG. 9A shows the lateral impurity concentration profile of a portion ofthe n-type diffused source/drain layer 20 which is taken along the lineIXa-IXa in FIGS. 11A, 11C and 11D.

As described above, according to the fourth embodiment, in the stepshown in FIG. 10C, the amorphous layer 21 is formed in the n-type sourceand drain formation region by implantation of germanium ions, and thenin the step shown in FIG. 10D, the p-type ion implanted layers 19A andthe n-type implanted source and drain layers 20A are formed. Thus, byforming the amorphous layer 21 in the n-type source and drain formationregion, channeling of arsenic in forming the n-type implanted source anddrain layers 20A is suppressed. Consequently, the n-type implantedsource and drain layers 20A having shallow impurity profiles can beformed.

Thereafter, in the step shown in FIG. 11A, subsequently to crystalrestoration by the first extremely low-temperature thermal treatment,the second rapid thermal annealing carries out activation. Thereby, theimplanted impurity can be activated with this impurity hardly diffused.As described above, during this activation, ionized donor and acceptoratoms are electrically attracted to each other by the thermal treatmentto produce an ion pair. By this, ionized arsenic in the n-type implantedsource and drain layers 20A and ionized indium in the p-type ionimplanted layers 19A produce an ion pair, which suppresses transientenhanced diffusion of arsenic. Therefore, the n-type diffused source anddrain layers 20 can be formed which have a shallower junction depth thanthe case where only an n-type impurity is implanted.

Thus, the ion pair suppresses arsenic diffusion, which eliminates thenecessity to set the second rapid thermal annealing performedsubsequently to the first extremely low-temperature thermal treatmentand performed for activation for forming the n-type diffused source anddrain layers 20 at a temperature higher than required. Also, thenecessity to keep the heated state for a long time even after completionof the heating is eliminated, so that the activation process can becarried out with a low thermal budget. The n-type diffused extensionlayer 16 is formed after formation of the n-type diffused source anddrain layers 20, which also avoids the situation in which by the thermaltreatment in the step of activating the n-type impurity for source anddrain formation, redistribution of the impurity occurs in the n-typediffused extension layer 16 having once been formed shallowly, therebymaking the junction depth thereof deep.

Moreover, as shown in FIG. 11A, by performing the first extremelylow-temperature thermal treatment immediately after the implantation ofarsenic ions into the source and drain formation region, the crystal ofthe amorphous layer 21 formed by high-dose implantation forpre-amorphization can be restored. In the first extremelylow-temperature thermal treatment, the thermal treatment temperature issufficiently low. Therefore, only point defects in the semiconductorsubstrate 11 disappear by diffusion and recombination, impuritydiffusion resulting from transient enhanced diffusion hardly occurs, andonly regrowth of the amorphous layer 21 proceeds. As mentioned above,under thermal treatment temperatures of about 400 to 700° C., morelimitedly, about 400 to 600° C., solid phase regrowth occurs in theamorphous layer 21. Thus, the junction of arsenic and indium implantedinto the source and drain formation region can keep a shallow junctiondepth that is almost the same as that made at the time of the respectiveion implantations. During restoration of the crystal of the amorphouslayer, the layer is in the meta-stable state in which the solubilitylimit of the contained impurity is higher than that of the impuritycontained in the crystal layer. Therefore, activation of the implantedions in the amorphous layer is enhanced as compared to the case wherethe crystal layer is subjected to the thermal treatment with the sametemperature.

Furthermore, in the fourth embodiment, by implanting in advance ions ofthe element belonging to the group IV into the source and drainformation region to form the amorphous layer 21, the source and drainformation region can be amorphized selectively and positively. That isto say, the source and drain formation region is pre-amorphized byangled implantation before formation of the n-type implanted source anddrain layers 20A, whereby not only channeling in the depth direction ofthe implanted arsenic ions can be suppressed, but also laterallystruggling intrusion of arsenic ions into the region below the gateelectrode 15 resulting from channeling in the <110>-oriented zone axiscan be suppressed.

Moreover, it is known that indium strongly segregates to a dislocationloop defect layer. Therefore, by forming the p-type ion implanted layers19A with indium ions implanted therein within the n-type implantedsource and drain layers 20A with arsenic ions implanted, the indium istrapped into the dislocation loop defect layer. This suppressestransient enhanced diffusion of arsenic contributing to release ofinterstitial silicon from the dislocation loop defect layer.

As is apparent from the above, the n-type diffused source and drainlayers 20 with shallow junctions can be formed certainly whileredistribution of the impurity in the n-type diffused extension layer 16is suppressed.

Moreover, indium ions with a relatively large mass number are used forformation of the p-type diffused channel layer 12. Therefore, a regionof the p-type diffused channel layer 12 located around the substratesurface has a decreased impurity concentration, while a region thereoflocated slightly deeper than the substrate surface has an increasedimpurity concentration. That is to say, a retrograde impurity profilecan be provided in this layer. This prevents a decrease in carriermobility mainly resulting from impurity dispersion and thereforeminimizes manifestation of short channel effect. As a result, thetransistor in the device can be miniaturized reliably.

Also in the second embodiment, angled implantation of germanium ions orsilicon ions may be performed when the source and drain formation regionis formed with the amorphous layer 21.

In the first to fourth embodiments, an indium ion is used as an impurityion of the p-type diffused channel layer 12. Instead of this, a boronion or an ion of an element heavier than boron and serving as a p-typeelement may be used thereas, or these ions may be used together.Furthermore, an element belonging to the group 3B and having a largermass number than indium may be used. In addition, silicon oxide is usedfor the gate insulating film 12, but an oxynitride film or an insulatingfilm of high dielectric such as hafnium oxide or hafnium silicate may beused therefor.

In the first to fourth embodiments, description has been made using then-channel type MIS transistor as the semiconductor device. Instead ofthis, the device used may be a p-channel MIS transistor. In the case ofthe p-channel MIS transistor, as a p-type impurity ion forming p-typediffused source and drain layers, use can be made of a boron ion, anindium ion, or the like, and as an n-type impurity combining with thep-type impurity ion to produce an ion pair, use can be made of a group5B element such as an arsenic ion, an antimony (Sb) ion, or a bismuth(Bi) ion.

In the first to fourth embodiments, silicon oxide is used for the gateinsulating film 14, and polysilicon or polymetal is used for the gateelectrode 15. Alternatively, a so-called gate replacement may be carriedout in which the gate electrode 15 and the gate insulating film 14 areremoved by etching after formations of the n-type diffused source anddrain layers 20 and the n-type diffused extension layer 16, and then thegate electrode structure is substituted by employing the gate insulatingfilm 14 made of a high dielectric film of silicon oxynitride, hafniumoxide, or the like and the gate electrode 15 made of a metal film oftungsten, titanium, or the like.

As described above, in the semiconductor device and the method forfabricating the device according to the present invention, implantationof an impurity with an opposite conductivity type to the impurity in thediffused source and drain layers into the diffused source and drainlayers exerts the following effects: transient enhanced diffusion of theimpurity forming the diffused source and drain layers can be suppressedby a low thermal budget, diffused source and drain layers with anabrupt, shallow junction can be formed, and impurity distribution in thediffused extension layer can be suppressed. Consequently, thesemiconductor device according to the present invention is useful for aminiaturizable semiconductor device and the like having a diffused layerwith a shallow junction and a low resistance.

1-5. (canceled)
 6. A method for fabricating a semiconductor device,comprising: the step (a) of sequentially forming a gate insulating filmand a gate electrode on a semiconductor layer of a first conductivitytype; the step (b) of forming sidewalls on side surfaces of the gateelectrode; the step (c) of subjecting the semiconductor layer to ionimplantation of a first impurity of the first conductivity type usingthe gate electrode and the sidewalls as a mask, thereby forming impurityimplanted layers of the first conductivity type in regions of thesemiconductor layer located below sides of the sidewalls; the step (d)of subjecting the semiconductor layer to ion implantation of a secondimpurity of a second conductivity type using the gate electrode and thesidewalls as a mask, thereby forming implanted source and drain layersof the second conductivity type in regions of the semiconductor layerlocated below the sides of the sidewalls; and the step (e) ofsubjecting, after the steps (c) and (d), the semiconductor layer to afirst thermal treatment, thereby diffusing the second impurity to formdiffused source and drain layers of the second conductivity type inregions of the semiconductor layer located below the sides of thesidewalls, wherein in the step (e), insides of the diffused source anddrain layers are formed with impurity implanted regions of the firstconductivity type, respectively, which are made by diffusing the firstimpurity with a lower impurity concentration than that of the diffusedsource and drain layers.
 7. The method of claim 6, further comprising,after the step (a) and before the step (b), the step (f) of subjectingthe semiconductor layer to ion implantation of a third impurity of thesecond conductivity type using the gate electrode as a mask, therebyforming implanted extension layers of the second conductivity type inregions of the semiconductor layer located below sides of the gateelectrode, the step (g) of subjecting the semiconductor layer to ionimplantation of a fourth impurity of the first conductivity type usingthe gate electrode as a mask, thereby forming implanted pocket layers ofthe first conductivity type in regions of the semiconductor layerlocated below the sides of the gate electrode, and the step (h) ofsubjecting, after the steps (f) and (g), the semiconductor layer to asecond thermal treatment, thereby diffusing the third impurity to formdiffused extension layers of the second conductivity type in regions ofthe semiconductor layer located below the sides of the gate electrode,and simultaneously diffusing the fourth impurity to form diffused pocketlayers of the first conductivity type in regions of the semiconductorlayer located below the diffused extension layers, wherein the impurityconcentration of the impurity implanted region is higher than that ofthe diffused pocket layer.
 8. The method of claim 6, further comprising,before the step (a), the step (i) of subjecting the semiconductor layerto ion implantation of a fifth impurity of the first conductivity typeto form an implanted channel layer of the first conductivity type in thesemiconductor layer, and then subjecting the semiconductor layer to athird thermal treatment, thereby diffusing the fifth impurity to form adiffused channel layer of the first conductivity type in thesemiconductor layer, wherein the impurity concentration of the impurityimplanted region is higher than that of the diffused channel layer. 9.The method of claim 6, further comprising, after the step (b) and beforethe steps (c) and (d), the step (j) of subjecting the semiconductorlayer to ion implantation of a sixth impurity using the gate electrodeand the sidewalls as a mask, thereby forming amorphous layers in regionsof the semiconductor layer located below sides of the sidewalls.
 10. Themethod of claim 9, wherein the sixth impurity is a group IV element. 11.The method of claim 6, wherein ion implantation of the second impurityis conducted at an implantation projected range equal to or larger thanthe implantation projected range of the first impurity.
 12. The methodof claim 6, wherein the first impurity is indium.
 13. The method ofclaim 6, further comprising, after the step (d) and before the step (e),the step (k) of performing an extremely low-temperature thermaltreatment of a level at which the implanted impurity does not diffuse,thereby restoring crystal damages due to the ion implantation.
 14. Themethod of claim 13, wherein the heating temperature of the extremelylow-temperature thermal treatment in the step (k) is from 400 to 700° C.inclusive.
 15. The method of claim 6, further comprising: the step (l)of removing, after the step (e), the sidewalls and then subjecting thesemiconductor layer to ion implantation of a third impurity of thesecond conductivity type using the gate electrode as a mask, therebyforming implanted extension layers of the second conductivity type inregions of the semiconductor layer located below sides of the gateelectrode; the step (m) of subjecting the semiconductor layer to ionimplantation of a fourth impurity of the first conductivity type usingthe gate electrode as a mask, thereby forming implanted pocket layers ofthe first conductivity type in regions of the semiconductor layerlocated below the sides of the gate electrode; and the step (n) ofsubjecting, after the steps (l) and (m), the semiconductor layer to asecond thermal treatment, thereby diffusing the third impurity to formdiffused extension layers of the second conductivity type in regions ofthe semiconductor layer located below the sides of the gate electrode,and simultaneously diffusing the fourth impurity to form diffused pocketlayers of the first conductivity type in regions of the semiconductorlayer located below the diffused extension layers, wherein the impurityconcentration of the impurity implanted region is higher than that ofthe diffused pocket layer.
 16. The method of claim 9, wherein in thestep (j), the sixth impurity is implanted by angled implantation havinga predetermined angle with respect to the normal to a main surface ofthe semiconductor layer.